Extra Bits on SRAM and DRAM Errors - More Data from the Field

Several recent publications have shown that memory errors are common in high-performance computing systems, due to hardware faults in the memory subsystem. With exascale-class systems predicted to have 100-350x more DRAM and SRAM than current systems, these faults are predicted to become more common. Therefore, further study of the faults experienced by DRAM and SRAM is warranted. In this paper, we present a field study of DRAM and SRAM faults in Cielo, a leadershipclass high-performance computing system located at Los Alamos National Laboratory. Our DRAM results show that vendor choice has a significant impact on fault rates. We also show that command and address parity on the DDR channel, a required feature of DDR3 memory, is beneficial to memory reliability. For SRAM, we confirm that altitude has a significant impact on SRAM fault rates, and that the majority of these SRAM faults are caused by high-energy particles. We also show, contrary to what might be expected, that the majority of uncorrected SRAM errors are due to singlebit strikes. Finally, we examine the impact of fault and/or error rates when scaling node capacities to a potential future exascaleclass systems.